Intel ships multi-die chips ahead of schedule – to the US military
Intel this week said the prototype multi-die chips it was commissioned to build for the US Department of Defense are now ready more than a year ahead of schedule.
The x86 giant’s emphasis on over delivering seems to reflect a newfound self awareness that it doesn’t exactly, for now, have the best reputation for shipping products on time, something the Department of Energy’s Argonne National Laboratory knows well.
The lab’s Aurora Supercomputer, which will use Intel’s HBM-toting Sapphire Rapids Xeons and Ponte Vecchio GPUs, has been pushed back repeatedly since 2017 by Intel’s inability to ship chips on time. Work on the system, which was supposed to come online in 2021, is still ongoing.
Compared to Aurora, the prototypes Intel built for the US DoD under its State-of-the-Art Heterogeneous Integrated Packaging (SHIP) program are nowhere near as complex. However, they do take advantage of many of the same technologies underpinning the super.
Under the SHIP program, Intel was tasked with developing methods for placing and connecting CPUs, FPGAs, ASICs and government-developed chiplets all within the same processor packaging. The idea being that Intel designs some parts, others provide the other blocks, and it all comes together on multiple separate dies within the same chip.
This multi-die, chiplet approach has become widespread in the years since AMD launched its Ryzen, Epyc, and Threadripper processor families, which packed multiple compute and IO dies together on a single package to achieve higher core counts and better yields. Intel has since adopted this technology in its latest generation of CPUs and GPUs.
Generally speaking, Intel and AMD have used their architectures to glue together similar sorts of dies – CPU cores, IO controllers – while the Pentagon wants to use Intel’s embedded multi-die interconnect bridge (EMIB) and Foveros 3D packaging technologies to bring together very different kinds of chip, linking CPUs to application-specific designs. The DoD supplies these sensitive military chip designs, while Intel supplies the general purpose compute components, manufactures, and stitches them all together.
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One of the DoD’s goals under the program was to “diversify their supply chain.” And since Intel is one of the few leading-edge foundry operators in the US that also has experience with multi-die compute architectures, it was a natural choice.
While Intel says it has just delivered the first prototypes, its involvement in the SHIP initiative is far from over. The fab giant says it will continue to develop prototypes of multi-die packages, while also working to improve chiplet size, weight, power, and performance.
Cynics among you might also say Intel was more than a year ahead of schedule because, given the Xeon goliath’s aforementioned track record with Aurora, the US military set Intel a very generous deadline, which it was able to meet and so victory here is nothing too special. Of course, we’d never suggest such a thing. Intel’s gotta start catching up at some point, right?
Heterogeneous chiplets for the rest of us
While the Pentagon worked with Intel to achieve its goals, for heterogeneous chiplet architectures to gain mainstream viability chipmakers are going to have to agree on standards for how they should talk to each other.
Until recently, most multi-die interfaces — like those developed by AMD, Intel, and others — have been designed around their own products. For example, AMD wasn’t trying to get its GPU dies to talk to Intel’s CPU dies — well, except for that one time that they did.
More recently, several leading chipmakers have come together in support of an industry standard for die-to-die communications called Universal Chiplet Interconnect Express (UCIe). The spec is intended to be a common language for chiplets and could eventually allow a variety of novel chip combos. ®